1. Field of the Invention
The present invention relates to a semiconductor device, particularly to a semiconductor device on which a defect detection test is performed.
2. Description of the Background Art
Due to the recent progress in semiconductor manufacturing technology, a logic-merged memory has been implemented that has, on the same chip, a logic circuit and a memory and data can be communicated between the logic circuit and the memory. Since such a logic-merged memory can have an improved transfer rate between the logic circuit and the memory, high-speed data processing can be achieved.
In the logic-merged memory, in terms of high-speed operation and power consumption for example, a memory cell configured with a thin-film transistor for logic applications that can provide high performance with a low voltage is used. As for the memory cell structure, a so-called twin cell structure comprised of, for example, two MOS transistors (access transistors) and two capacitors is employed. Further, in most cases, a memory cell is formed with a P-channel MOS transistor whose power consumption due to gate leakage current or the like is approximately one-third as high as that of an N-channel MOS transistor. The thin-film transistor is a transistor having a lower operating voltage relative to an input/output circuit for external elements of the semiconductor device. For example, relative to the operating voltage 3.3 V of the input/output circuit, the operating voltage of the thin-film transistor is 1.2 V.
Here, a description is given about a reliability test for such a device as logic-merged memory. Generally, device failures are roughly divided into three periods that are initial failure period, random failure period and wear-out failure period in order of time. The initial failure refers to a failure occurring immediately after the start of use, due to deficiencies in device manufacturing process. For example, the initial failure includes the state in which the resistance value of a metal interconnection is larger than a standard value and the state in which a memory cell has large leakage current. Such states are not critical defects at the start of use of the device. These defects relevant to tolerances that are failures becoming critical as the device is used belong to the initial failure. The initial failure rate rapidly decreases with time, and subsequently the random failure period starts in which a low failure rate lasts for a certain long period. Then, the wear-out failure period starts in which the end of useful life of the device is being reached and the failure rate sharply increases. It is desirable that the device is used in the random failure period, and the random failure period corresponds to the useful lifetime of the device. Therefore, in order to improve the device reliability, it is required that the random failure period lasts for a long time and the failure rate in the random failure period is low and constant.
In order to remove initial failures in advance, screening is generally carried out by performing accelerated operation aging on the device for a certain time so as to remove defectives. For effectively performing the screening in a short period of time, it is desirable that the initial failure rate immediately decreases in a short period of time and the random failure period starts earlier. Currently, as one of screening methods, high-temperature operation test (burn-in test) is generally conducted.
Generally, in normal operation, an external voltage according to specifications is supplied to the semiconductor device for reading data and writing data for example. In contrast, in burn-in test, a higher external power supply voltage than that in normal operation is supplied to the device. Accordingly, high electric field stress is applied to the device and thus the degree of acceleration of the burn-in test is increased.
In particular, for the state of wafer, wafer level burn-in test is effective. The wafer level burn-in test is a method by which a dielectric film of a transistor or the like can be directly evaluated using the actual device. Various factors of defectives such as short circuit between interconnections can be revealed in accelerated manner by applying high temperature and high electric field stress.
In the case where the memory cell stores H data (data having a logically high level) and the access transistor is OFF for example, application of the same voltage as H data to the gate of the access transistor could be insufficient to cause electric charges stored in the memory cell capacitor to flow out from the gate, resulting in flow of off-leakage current. This is a problem for a thin film transistor having a small gate voltage for turning the transistor ON. Therefore, when the access transistor is OFF, a voltage higher than the level of H data has to be supplied to the gate of the access transistor.
Further, for the logic-merged memory having a memory cell whose access transistor is P-channel MOS transistor, a negative voltage has to be supplied to the gate of the access transistor in order to write L data (data having a logically low level) to the memory cell.
Therefore, within the device, it is necessary to generate a voltage higher than the level of H data as well as a negative voltage from an external power supply voltage and supply the generated voltages to the memory cell. Then, for example, excessive stress could be imposed between electrodes, for example, between the gate and drain and between the gate and source of the transistor provided in the output stage of the supply voltage to the memory cell for example.
Furthermore, since the external power supply voltage in burn-in test is larger than that in normal operation as described above, further excessive stress is imposed on the transistor, which could cause the gate oxide film of the transistor to be broken.
In contrast, a semiconductor device disclosed in Japanese Patent Laying-Open No. 10-092200 (Patent Document 1) is configured to accelerate initial defects by applying a cell plate voltage in burn-in test that is different from the one in normal operation. However, no measures are taken to address malfunctions due to a larger voltage difference between two voltages supplied to a memory cell or the like. Further, a semiconductor device disclosed in Japanese Patent Laying-Open No. 2002-298599 (Patent Document 2) is configured to accelerate initial defects by making switch between a plurality of internal power supplies in normal operation and burn-in operation. However, no measures are taken to address malfunctions due to a voltage difference between two voltages supplied to a memory cell or the like.
Therefore, for the semiconductor devices disclosed in Patent Documents 1 and 2, it is necessary to provide a lower external power supply voltage in burn-in test for avoiding breakage of the thin film transistor. Thus, high electric field stress cannot be applied to the device, resulting in the problem that the burn-in test takes a long time. In addition, since the external power supply voltage cannot be increased, stress for revealing initial failures cannot be applied to the gate oxide film for example of the transistor, resulting in the problem that initial defectives cannot be removed sufficiently.
Moreover, a voltage different from that in normal operation may be externally supplied in burn-in test so as to apply high electric field stress to the device and thereby shorten the burn-in test time. However, a pad for applying a power supply voltage except for the external power supply voltage for normal operation has to be provided, which could increase the circuit size and area.